fetch execute cycle
Overview
# The Fetch-Execute Cycle ## Summary The Fetch-Execute Cycle describes the fundamental process by which a CPU retrieves instructions from memory (fetch), decodes them to determine the required operation (decode), and carries out the instruction (execute). This iterative cycle involves key components including the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), and Accumulator, with the Control Unit orchestrating data flow via the system buses (address, data, and control buses). Understanding this cycle is essential for A-Level examinations, as questions frequently require students to trace instruction execution step-by-step, explain the role of specific registers, or analyze how different processor architectures affect performance. ## Exam Relevance This topic commonly appears in structured questions worth 6-10 marks requiring sequential explanation of cycle stages and register interactions, making it a high-yield revision
Core Concepts & Theory
The Fetch-Execute Cycle (also called the Fetch-Decode-Execute Cycle) is the fundamental process by which a CPU processes instructions stored in memory. It operates continuously while the computer is running, executing billions of cycles per second.
Key Components:
Program Counter (PC): A special register holding the memory address of the next instruction to be executed. It increments automatically after each fetch unless a jump/branch instruction alters it.
Memory Address Register (MAR): Holds the address of the memory location to be read from or written to during the current cycle.
Memory Data Register (MDR) or Memory Buffer Register (MBR): Temporarily stores data being transferred between the CPU and main memory.
Current Instruction Register (CIR): Stores the instruction currently being decoded and executed.
Accumulator (ACC): A general-purpose register used for arithmetic and logical operations, storing intermediate results.
The Four-Stage Cycle:
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FETCH: Copy address from PC to MAR → Increment PC → Copy instruction from memory location (addressed by MAR) into MDR → Transfer instruction from MDR to CIR
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DECODE: The Control Unit interprets the instruction in CIR, identifying the opcode (operation) and operand (data/address)
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EXECUTE: The identified operation is performed (e.g., ADD, LOAD, STORE, JUMP)
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RESET: Results are stored appropriately, and the cycle repeats
Cambridge Note: Exam questions frequently ask for step-by-step descriptions with register names. Always reference specific registers (PC, MAR, MDR, CIR) for full marks.
Detailed Explanation with Real-World Examples
Analogy: The Library Book Retrieval System
Imagine the Fetch-Execute Cycle as a librarian retrieving and processing book requests:
- Program Counter: A numbered list of book requests; the librarian notes which request is next
- MAR: The specific shelf location written on a note
- MDR: The trolley carrying the book between shelf and desk
- CIR: The request form being read at the desk
- Execute: Actually fulfilling the request (stamping, filing, etc.)
The librarian checks their list (PC), writes down the shelf number (MAR), walks to that shelf, places the book on the trolley (MDR), brings it to the desk, reads the request form (CIR), then processes it (EXECUTE). They then move to the next request number.
Real-World Application: Smartphone Gaming
When playing a mobile game, every frame rendered involves millions of fetch-execute cycles:
- FETCH: The CPU retrieves game instructions ("check if screen was touched")
- DECODE: Interprets this as a conditional branch instruction
- EXECUTE: Compares touch sensor data; if touched, jumps to "fire weapon" code
Modern processors execute 3-5+ billion cycles per second (GHz). A 3GHz processor completes 3,000,000,000 fetch-execute cycles every second, enabling smooth 60fps gameplay.
Pipelining Enhancement: Advanced CPUs don't wait for one cycle to complete. While one instruction executes, the next fetches simultaneously—like multiple librarians working on different stages of different requests. This dramatically improves throughput.
Worked Examples & Step-by-Step Solutions
**Example 1: Trace the Fetch-Execute Cycle** (6 marks) *Question:* Describe the fetch stage of the fetch-execute cycle, naming all registers involved. *Model Answer:* 1. The address in the **Program Counter (PC)** is copied to the **Memory Address Register (MAR)** [1 mark] 2. The **PC is increment...
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Key Concepts
- Program Counter (PC): A register that holds the memory address of the next instruction to be fetched.
- Memory Address Register (MAR): A register that holds the address of the memory location currently being accessed.
- Memory Data Register (MDR): A register that temporarily stores data or instructions read from or written to memory.
- Current Instruction Register (CIR): A register that holds the instruction currently being decoded and executed.
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Exam Tips
- →Be able to clearly describe each stage (Fetch, Decode, Execute) and the role of each register (PC, MAR, MDR, CIR, ACC) within each stage. Use specific register names in your explanations.
- →Practice drawing a diagram of the Fetch-Execute Cycle, showing the flow of data and addresses between the CPU components and memory. Label all registers and buses.
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